1. Field of the Invention
The present invention relates generally to an image sensing apparatus which acquires digitized image data through a sensing device. More particularly, the invention relates to an improvement in the speed of processing image data by an image sensing apparatus.
2. Description of the Related Art
Computer systems like personal computers and word processors are typically equipped with an image scanner which scans an original target and reads the target's image information. Recently, it has been proposed to install electronic still cameras into computer systems in order to acquire image information of a three-dimensional object. Electronic still cameras have an image sensing device which generates image signals, and most of them finally supply image information as "digital data" to computer systems through a digitized image signal processor.
FIG. 1 is a block diagram showing an image sensing apparatus (electronic still camera) which is capable of generating one screen of image information in the form of digital data (i.e., image data). The image sensing apparatus comprises a charge couple device (CCD) image sensor 101, a driving circuit 102, a timing controller 103, an analog signal processor 104, an A/D (Analog/Digital) converter 105, and a digital signal processor 106. The CCD image sensor 101 has a light-receiving surface on which a plurality of light-receiving elements are aligned in a matrix form. The individual light-receiving elements produce information charges in response to light irradiated on the light-receiving surface. In this manner, the light-receiving elements store the produced information charges. A color filter having a plurality of specific color components arranged in a mosaic pattern is attached to the front portion of the light-receiving surfaces so that the individual light-receiving elements are associated with the respective color components.
The driving circuit 102 produces a multi-phase clock pulse signal in response to horizontal and vertical scan timing signals received from the timing controller 103, and transmits this clock pulse signal to the CCD image sensor 101. The CCD image sensor 101 sequentially transfers the information charges stored in the individual light-receiving elements to the analog signal processor 104 in a line-by-line manner. At this time, the output section of the CCD image sensor 101 converts the information charges, stored in the individual light-receiving elements, to voltage values in accordance with the level of charge. The CCD image sensor 101 outputs the analog pixel signals having the converted voltage values.
Next, the analog signal processor 104 will perform signal processing, such as a sample and hold operation and gain control on the analog pixel signals (received from the CCD image sensor 101) and supplies the analog pixel signals in a predetermined format to the A/D converter 105. If the CCD image sensor 101 outputs an analog pixel signal having a reference level and a signal level that is alternately repeated, for example, the difference between the reference level and the signal level will be acquired in the sample and hold operation. Under the gain control, the gains of the analog pixel signals may be adjusted in such a way that the average level of one screen of analog pixel signals falls within a predetermined proper range.
The A/D converter 105 is configured to convert the analog pixel signals to digital pixel signals in synchronism with the signal output operation of the CCD image sensor 101. In this manner, A/D converter 105 may supply the digital pixel signals to the digital signal processor 106. By way of example, the digital pixel signals correspond to the respective light-receiving elements of the CCD image sensor 101.
The digital signal processor 106 performs a color-component separation for the digital pixel signals, white balance adjustment and edge enhancement or the like to produce image data which includes luminance information and color difference information. Formally, luminance data Y representing the luminance and two kinds of color difference data U and V respectively, represent the difference between the luminance component and red component, and the difference between the luminance component and blue component. These components are therefore used for processing image data representing a color video image. The image data consisting of three kinds of data Y, U and V is transmitted to the computer system which outputs in the image-information scanning order of the CCD image sensor 101.
The above-discussed image sensing apparatus should face the demand for smaller and lighter apparatuses and reduce the number of components which translates to lower costs. In general, therefore, the analog signal processor 104 and digital signal processor 106 are designed as integrated circuit devices and are arranged together with the CCD image sensor 101 on a single circuit board.
The digital signal processor 106 typically needs memory having a predetermined capacity to temporarily store several lines of light-receiving pixel data. When one line consists of 640 pixels, and pixel data consists of eight bits, for example, the memory should have a capacity of approximately 40 K (640.times.8.times.8) bits to store eight lines of pixel data. The memory with such capacity is typically implemented together with the aforementioned digital signal processor on a single chip. Unfortunately, implementing these functions on a single chip will result in an increased need for additional chip area, thus resulting in increased manufacturing costs. Generally, therefore, the digital signal processor 106 and the memory are integrated on separate chips and are interconnected through a circuit board. However, this structure compels both the digital signal processor 106 and the memory to exchange a vast amount of pixel data at high speeds and requires that they have multiple input/output terminals. When 8-bit pixel data for eight pixels are exchanged in parallel, for example, 64 input/output terminals will be needed. This restriction complicates the interconnection structure on the circuit board and increases the power consumed by the operation of input/output buffers provided at the input/output terminals. As can be appreciated, this increases manufacturing cost for the circuit board, and the increased consumption of power shortens the operable time of an electronic still camera which often uses a battery as its power source. It is also possible to serially exchange pixel data between the digital signal processor 106 and the memory. However, as the amount of pixel data increases, the time needed to exchange the pixel data will become longer and the speed at which this exchange takes place will become slower. Consequently, this restricts the arithmetic operation of the digital signal processor 106, resulting in slower data processing.
There has been proposed an electronic still camera equipped with a recording medium, such as a non-volatile semiconductor memory or a magnetic disk, which temporarily stores the obtained image data before supplying the image data to a computer system. A computer equipped with such an electronic still camera can selectively read only necessary image data from the recording medium to process it. To ensure recording of a greater amount of image data, electronic still cameras are equipped with a recording apparatus which records image data on a recording medium after compression.
As shown in FIG. 2, the recording apparatus comprises a raster block converter 107, a encoder/decoder 108 and a data recording circuit 109. The raster block converter 107 converts the order of image data from the digital signal processor 106 to the optimal order for the processing in the encoder/decoder 108. This raster block converter 107 typically has sufficient memory to store several lines of image data, and reads image data from the memory in an order different from the writing order to thereby convert the aligning order of the image data. The raster block converter 107 stores the image data output from the digital signal processor 106 line by line in accordance with the scanning order of the CCD image sensor 101 and supplies the image data to the encoder/decoder 108 block by block which consists of given numbers of rows and columns.
The encoder/decoder 108 produces image data which has been compressed in block units, each unit consisting of a given numbers of rows and columns. In other words, the encoder/decoder 108 collectively stores several lines of image data in the memory and executes compression block by block according to a predetermined algorithm to produce compressed image data.
The encoder/decoder 108 performs decompression of the compressed image data (i.e., processing opposite to the compression) to restore the original image data. The computer system receives the reproduced image data block by block from the encoder/decoder 108. A display device of the computer system receives, line by line, image data whose aligning order has been converted by the raster block converter 107. The data recording circuit 109 is; comprised of a non-volatile semiconductor memory, which records the compressed image data corresponding to a plurality of screens. It is therefore apparent from the above discussion that the implementation of the raster block converter 107 will further increase the manufacturing cost of the image sensing apparatus.